logical state中文是什么意思

发音:

中文翻译
造句

逻辑状态

logical adj. 1.逻辑的，逻辑上的；逻辑学上的。 2.合乎逻 ...
state n. 1.〔常作 S-〕国，国家；〔通例作 S-〕(美国 ...
be logical 合乎逻辑
logical adj. 1.逻辑的，逻辑上的；逻辑学上的。 2.合乎逻辑的。 3.逻辑上必然的。 logical constants 逻辑常词[常项]。 logical necessity 逻辑的必然性。 a logical argument 条件分明的论证。 a logical process 合理的程序，合乎逻辑的[必然的]过程。 the logical result 必然的结果。 adv. -ly ,-ness n.
logical and 逻辑与
logical if 逻辑若
logical not 逻辑非
logical or 逻辑或
logical-in 逻辑归入
the logical 合选辑之歌
in a state 处于糟糕、混乱或不整洁的状态
in a state of 处于……的状态
in state 本州的; 正式地, 庄重地
on state 导通状态; 接通的; 通态
state‘s will 国家意志
will of the state 国家意志
a logical impossibility 逻辑上不可能的事
a logical mind 善于推理的头脑
add, logical 逻辑加
architecture, logical 逻辑（体系）结构
boolean-logical 布尔逻辑的
compare logical 比较逻辑
connective logical 逻辑连接号
infra-logical 逻辑下的

"查查词典"手机版

千万人都在用的超大词汇词典翻译APP

例句与用法

To change a physical or logical state to its opposite
将一种物理状态或逻辑状态变成它的相反的状态。
Flags may have one of two logical states , true or false . programs that use flags as arithmetic operands have an environmental dependency
旗标可以有两个逻辑状态之一,真或假.使用旗标作为计算操作的程式有环境相依性
By exploring the characters of dynamic power supply currents of digital circuits using spice , this paper analyzed the relation between iddt and the switching activities when a circuit changes from one logical state to another
本文通过spice实验研究数字电路动态电流的特性，分析了数字电路的动态电流与电路逻辑状态转变之间的关系。
While programs in the java language are theoretically immune from " memory leaks , " there are situations in which objects are not garbage collected even though they are no longer part of the program s logical state
虽然用java语言编写的程序在理论上是不会出现“内存泄漏”的，但是有时对象在不再作为程序的逻辑状态的一部分之后仍然不被垃圾收集。
The thesis also introduces the virtual instrument ’ s concept , system architecture , etc . the development of virtual instrument ’ s application software is discussed in detail . it includes virtual instrument software architecture ( visa ) , and virtual instrument ’ s software platforms . the thesis discusses the principle and mechanism of work of the simulation of embedded system . by comparing with the principle of traditional logical analyzer , it draw a conclusion that the virtual logical analyzer will work in synchronous way when it is used for both logical state analyzer and logical time analyzer . the thesis
论文接着探讨了嵌入式仿真平台的原理和工作机制,通过与传统逻辑分析仪原理的比较,得出了嵌入式仿真平台下逻辑分析仪无论是做定时分析,还是做状态分析都工作在同步方式下;并重点剖析了探头原理,采样定理和毛刺,数据的建立和保持时间等逻辑分析仪的重要技术指标,得出了虚拟环境对虚拟逻辑分析仪的功能和各项技术指标的影响,还提出了流水线状态表的思想和实现机制。
In addition to the normal functional interface of a component , by adding a test interface that exposes the logical states of the component , a tester can dynamically monitor and capture states information and service calling sequence of the component during testing
更进一步，在进行组件集成测试时，本文提出了组件内置测试机制和一种提高组件可测试性的方法，通过对各交互组件进行封装并扩展测试接口，达到在测试时动态监视和捕捉组件状态和服务调用序列信息的作用。